Application Notes are designed to help designers implement high performance, persistent MRAM in their solutions. These documents bring the knowledge and expertise of Everspin engineers directly to those that can benfit the most as they create products or applications based on MRAM.
ECC Design Considerations for STT-MRAM
To achieve a robust and reliable persistent memory design with STT-MRAM, designers need to also consider the internal architecture of STT-MRAM devices. In this application note we will cover implementation of Error Correcting Code (ECC) integrated into the STT-MRAM chip that helps ensure a low bit error rate (BER) for reliable designs.
ST-DDR3 Design Guide for Xilinx FPGA Controllers
Spin-Transfer Torque Magneto-resistive Random Access Memory (STT-MRAM) is a technology that delivers performance, persistence and durability as DDR3-like memory called ST-DDR3. With an interface that is designed around JEDEC standards, systems can utilize STT-MRAM in their designs with the described modifications to the memory controller to comprehend the persistence of STT-MRAM. This document will help engineers understand how to enable a Xilinx FPGA memory controller to communicate with persistent ST-DDR3 memory.
Utilizing Everspin STT-MRAM in Enterprise SSDs
This application note explores the SSD architecture benefits of employing Everspin ST-MRAM on the DDR bus of the SSD controller to provide a high speed, non-volatile write buffer in order to reduce power fail energy storage while increasing performance and storage density.
Accelerating Fintech Applications with Lossless and Ultra-Low Latency Synchronous Logging using nvNITRO
Financial Technology (FinTech) companies are looking for performance increases that still enable them to remain in compliance by protecting data. The nvNITRO accelerator with MRAM memory can increase performance 9X by dramatically reducing latency, all while protecting the data with persistence and endurance.