Datasheet for MR0A08B, 1Mb, Parallel IO MRAM
Product Change Notices (PCNs)
Product Discontinuance of 32-SOIC Package
PCN1893 ALTERNATIVE FORMAT FOR TRACE CODES ON PACKAGE MARKING
Beginning December 30, 2011, Everspin may use an alternative Trace Code marking format interchangeably with the existing format. The existing format identifies fabrication site, assembly site, final test site and wafer lot, year and work week. The alternative format will identify the assembly site and wafer lot, year and work week. Affects all Everspin products and packages.
Add ASE as a qualified assembly subcontractor for 256Kb and 1Mb MRAM in TSOP2 packages
Add ASE (in addition to Freescale KLM) as a qualified assembly subcontractor.
EST02880 Magnetic Immunity for Everspin MRAM 073115.pdf
Replacing the CypressCY14B101LA-xx nvSRAM with Everspin's MR0A08Bxxx MRAM
Considerations for replacing nvSRAM with MRAM
Comparing Technologies FRAM vs. MRAM
Compares FRAM memory technology with Everspin's MRAM technology.
Approximating the Magnetic Field When Using Everspin MRAM
How to create an approximation of the magnetic field strength surrounding an MRAM
technical articles & white papers
MRAM Improvements to Automotive Non-Volatile Memory Storage
Automotive powertrain modules use flash memory technology to retain critical control and diagnostic information during power off (keep-alive memory (KAM) and non-volatile memory (NVM)). Complex software must be designed to maximize the lifecycle of these devices because they have a limited number of write cycles. MRAM (Magneto resistive Random Access Memory) has the potential to eliminate this complexity and make the process of managing KAM and NVM easier and more robust. This paper demonstrates using off-board MRAM devices with a next generation of powertrain microprocessor. The prototype boards integrating the latest powertrain microcontroller, with the Everspin MRAM MRA16A (2 pcs of x16 bits) and MR2xH50 (@ a SCK 40MHz) chips were created. An investigation was performed evaluating the MRAM capabilities for storing and retrieving data during simulated key-off and key-on events.
Toggle and Spin-Torque MRAM: Status and Outlook
Article by J.M. Slaughter, et.al., of Everspin Technologies
MR0A08BYS35 IBIS File
Ibis model for part MR0A08BYS35.
MR0A08B VERILOG Model
This is the VERILOG model of the MR0A08B. MR0A08B.V is the abstracted model of a 128K x 8 MRAM. The following is contained in the download:
1. Readme_MR0A08B - Overview
2. MR0A08B.V - Device Model
3. Config_MR0A08B.V - Configuration File
MR0A08B VHDL Model
This is the VHDL model of the MR0A08B. This is a high level abstraction of this product. The following is contained in the download: 1. Readme_MR0A08B 2. MR0A08B.vhdl - Device Model 3. Package_Utility - Standard Conversion Utilities 4. Benchtest.vhdl - Top Level Test Bench 5. MR0A08B_Driver.vhdl - Sample Test Vectors used for the Verification 6. MR0A08B.txt - Memory Initialization File
RoHS / REACH
QUA00417_Everspin Reach Statement_SVHC197_2-25-19.pdf
Everspin Reach Statement - 2019
QUA00417_Everspin Reach Statement 3_27_2018.pdf
Everspin REACH statement
Everspin RoHS compliance
EICC Product Level Master
EICC Company Level Master
Everspin CFSI_CMRT by Product 4.10_09232016.xls
Everspin CFSI_CMRT Company Level 4.10_09232016.xls
No Red Phosphorus content in Everspin products
Red Phosphorus Statement