Documents for EMD4E001G08G1-150CAS2R

Datasheets

Rev. 1.2 Effective Sep 3 2020

EMD4E001GAS2 Datasheet

EMD4E001GAS2 Datasheet

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Product Change Notices (PCNs)

Effective Oct 21 2021

PCN03043_CMOS_Fab_Supplier_Trace Code.pdf

Everspin is adding a character to the trace code on all Everspin products to identify CMOS wafer Fab supplier.

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application notes

Rev. 1.1 Effective Oct 15 2019

Enabling Xilinx FPGA Controllers for ST-DDR4 Persistent Memory

Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a persistent memory technology that delivers performance, persistence, and durability utilizing variants of industry standard interfaces.  Everspin has introduced STT-MRAM products that utilize a variant of the JEDEC standard DDR4 interface, called ST-DDR4, that encompasses the unique functionality required for full system support. This document will help engineers understand how to enable a Xilinx FPGA memory controller to communicate with persistent ST-DDR4 memory.

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Rev. 1.0 Effective Oct 11 2019

ST-DDR4 Change Table V1 0.pdf

This app note shows the names of the fifteen modules that require changes from the standard Xilinx MIG controller for a XCKU060-2FFVA1156E device.  When run properly, the example script will automate these changes for the user.

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Rev. 1.0 Effective Oct 11 2019

Xilinx ST-DDR4 TCL Script

Xilinx ST-DDR4 TCL script

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Rev. 1.3 Effective Feb 7 2018

Application Note Utilizing Everspin STT-MRAM in Enterprise SSDs

As Enterprise Solid State Drives (SSDs) continue to push the envelope in terms of system performance and smaller form factors, SSD solutions providers are facing greater challenges to increase performance and density while continuing to protect data-in-flight from power failures. NAND flash has not significantly increased in performance and the improvement in SSD performance is typically made by adding more parallel channels of flash. This increases the need for energy storage for power fail protection which in turn reduces space available for the storage array for a fixed form factor.

This application note explores the SSD architecture benefits of employing Everspin ST-MRAM on the DDR bus of the SSD controller to provide a high speed, non-volatile write buffer in order to reduce power fail energy storage while increasing performance and storage density.

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Rev. 1 Effective Sep 28 2015

EST02880 Magnetic Immunity for Everspin MRAM 073115.pdf

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Rev. 1 Effective Feb 1 2012

Approximating the Magnetic Field When Using Everspin MRAM

How to create an approximation of the magnetic field strength surrounding an MRAM

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technical articles & white papers

Rev. 1 Effective Jan 8 2010

Toggle and Spin-Torque MRAM: Status and Outlook

Article by J.M. Slaughter, et.al., of Everspin Technologies

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IBIS Model

Rev. 1.0 Effective Oct 15 2019

IBIS Model for ST-DDR4 ESMR1GV50_v1

IBIS Model for ST-DDR4

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verilog model

Rev. 1.0 Effective Oct 15 2019

Verilog File for ST-DDR4

Verilog File for ST-DDR4

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RoHS / REACH

Rev. 2.2 Effective Mar 31 2022

RMI_CRT_2.2_Everspin_170322 Cobalt 31 March 22.xlsx

Conflict Minerals Cobalt Template, March 31, 2022

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Effective Mar 31 2022

RMI_CMRT_6.1_Everspin_Company Level_March 31 2022.xlsx

Conflict Minerals Company Level Template, March 31, 2022

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Rev. 6.1 Effective Mar 31 2022

RMI_CMRT_6.1_Everspin_Product Level 31 March 22.xlsx

Conflict Minerals Product Level Template, March 31, 2022

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Effective Mar 2 2022

QUA00417_Everspin_reach.pdf

Everspin Technologies REACH Statement

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Effective Mar 2 2022

QUA02364_EverspinRoHS.pdf

Everspin Technologies RoHS Statement

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Rev. 1.0 Effective May 29 2020

Everspin Conflict Minerals Report Fiscal 2019.pdf

Everspin Conflict Minerals Report Fiscal 2019

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Rev. 4.20 Effective Dec 16 2016

EICC Product Level Master

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Rev. 4.20 Effective Dec 16 2016

EICC Company Level Master

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Rev. 1.0 Effective Jan 24 2014

Everspin_RoHS_Red_Phosphorus_Compliance.pdf

RoHS Red Phosphorous statement

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