Datasheet for MR2A16A, 4 Mb, Parallel IO MRAM
Product Change Notices (PCNs)
PCN02952 Add OSE Assembly Site for 1Mb(x16) and 4Mb (x8and x16) BGA Package.pdf
Everspin is adding OSE as a qualified assembly site for the 1Mb(x16) and 4Mb (x8 and x16) MRAM BGA package.
PCN1893 ALTERNATIVE FORMAT FOR TRACE CODES ON PACKAGE MARKING
Beginning December 30, 2011, Everspin may use an alternative Trace Code marking format interchangeably with the existing format. The existing format identifies fabrication site, assembly site, final test site and wafer lot, year and work week. The alternative format will identify the assembly site and wafer lot, year and work week. Affects all Everspin products and packages.
Burn-In, Final Test transferred to UTAC Taiwan for 256Kb, 1Mb, 4Mb Parallel IO and 256Kb and 1Mb Serial SPI MRAM
Burn-in, final test and end of line services are transferred from UTAC Singapore to UTAC Taiwan.
Thermal Resistance, Recommended reflow profile, package outline drawings for all 48-ball FBGA packages from Everspin
EST 2130 Comparing_Technologies_FRAM_vs_MRAM_AppNote.pdf
Comparing MRAM to FRAM
EST02880 Magnetic Immunity for Everspin MRAM 073115.pdf
Replacing Cypress CY14B104NA BA and ZS nvSRAMs with Everspin MR2A16A MRAM
Replacing the Cypress CY14B104NA-BA/ZS45XI nvSRAM with Everspin's MR2A16Axxx35 MRAM
Approximating the Magnetic Field When Using Everspin MRAM
How to create an approximation of the magnetic field strength surrounding an MRAM
technical articles & white papers
Cobham Toggle MRAM Quality and Reliability White Paper
Toggle MRAM Quality and Reliability Paper
A white paper discussing the reliability and qualification for Toggle MRAM components by Cobham
MRAM Improvements to Automotive Non-Volatile Memory Storage
Automotive powertrain modules use flash memory technology to retain critical control and diagnostic information during power off (keep-alive memory (KAM) and non-volatile memory (NVM)). Complex software must be designed to maximize the lifecycle of these devices because they have a limited number of write cycles. MRAM (Magneto resistive Random Access Memory) has the potential to eliminate this complexity and make the process of managing KAM and NVM easier and more robust. This paper demonstrates using off-board MRAM devices with a next generation of powertrain microprocessor. The prototype boards integrating the latest powertrain microcontroller, with the Everspin MRAM MRA16A (2 pcs of x16 bits) and MR2xH50 (@ a SCK 40MHz) chips were created. An investigation was performed evaluating the MRAM capabilities for storing and retrieving data during simulated key-off and key-on events.
Toggle and Spin-Torque MRAM: Status and Outlook
Article by J.M. Slaughter, et.al., of Everspin Technologies
MR2A16ACYS35 IBIS File
Ibis model for part MR2A16ACYS35.
MR2A16AYS35 IBIS File
Ibis model for part MR2A16AYS35.
MR2A16AVYS35 IBIS File
Ibis model for part MR2A16AVYS35.
MR2A16A VERILOG Model
This is the VERILOG model of the MR2A16A. MR2A16A.V is the abstracted model of a 256K x 16 MRAM. The following is contained in the download:
1. Readme_MR2A16A - Overview
2. MR2A16A.V - Device Model
3. Config_MR2A16A.V - Configuration File
4. testbench_MR2A16A.v - Test bench file
MR2A16A VHDL Model
This is the VHDL model of the MR2A16A. This is a high level abstraction of this product. The following is contained in the download:
2. MR2A16A.vhdl - Device Model
3. Package_Utility - Standard Conversion Utilities
4. Benchtest.vhdl - Top Level Test Bench
5. MR2A16A_Driver.vhdl - Sample Test Vectors used for the Verification
6. MR2A16A.txt - Memory Initialization File
RoHS / REACH
Everspin Technologies REACH Statement
Everspin Conflict Minerals Report Fiscal 2019.pdf
Everspin Conflict Minerals Report Fiscal 2019
Everspin Technologies RoHS Statement
EICC Product Level Master
EICC Company Level Master
Everspin CFSI_CMRT by Product 4.10_09232016.xls
Everspin CFSI_CMRT Company Level 4.10_09232016.xls
RoHS Red Phosphorous statement