Datasheets
MR4A08BUYS45 - MR4A16BUYS45 Data Sheet
MR4A08BUYS45 and MR4A16BUYS45 products data sheet
MR2xH40_Datasheet
Datasheet for MR2xH40, 4Mb Serial SPI MRAM
MR0D08B_Datasheet.pdf
Datasheet for MR0D08B, 1 Mb, Parallel IO, Dual Power Supply MRAM
MR2A08A_Datasheet.pdf
Datasheet for MR2A08A, 4 Mb, Parallel IO MRAM
MR4A08B_Datasheet.pdf
Datasheet for MR4A08B, 16 Mb, Parallel IO MRAM
MR0A16A_Datasheet.pdf
Datasheet for MR0A16A, 1 Mb, Parallel IO MRAM
MR2A16A_Datasheet.pdf
Datasheet for MR2A16A, 4 Mb, Parallel IO MRAM
MR4A16B_Datasheet.pdf
Datasheet for MR4A16B, 16 Mb, Parallel IO MRAM
MR25H256-MR25H256A_Datasheet.pdf
Datasheet for MR25H256/MR25H256A, 256K, Serial SPI MRAM
MR25H10_Datasheet.pdf
Datasheet for MR25H10, 1Mb Serial SPI MRAM
MR256A08B_Datasheet.pdf
Datasheet for MR256A08B, 256K, Parallel IO MRAM
MR256D08B_Datasheet.pdf
Datasheet for MR256D08B, 256 Kb, Parallel IO, Dual Power Supply MRAM
MR256DL08B_Datasheet.pdf
MR256DL08B, Dual Supply 32K x 8 MRAM
MR0DL08B_Datasheet.pdf
Datasheet for MR0DL08B, Dual Supply 128K x 8 MRAM
MR0A08B_Datasheet.pdf
Datasheet for MR0A08B, 1Mb, Parallel IO MRAM
Product Change Notices (PCNs)
PCN03000 Die Attach Material Change for 1Mb (x16) and 4Mb (x8 and x16) TSOP-44p Package from OSE.pdf
Product and Process Change Notification - Die Attach Material Change for 1Mb (x16) and 4Mb (x8 and x16) TSOP-44p Package. March 14, 2019
PCN02996 Add ChipMOS as a Subcontractor Assembly Site for the DFN package
PCN 02996 - Add ChipMOS as a subcontractor assembly site
PCN02997 Add UTAC Dongguan as a Subcontractor Assembly Site for the BGA-24 package
PCN02997 Add UTAC Dongguan as a Subcontractor Assembly Site for the BGA-24 package
PCN02967 Moisture Sensitivity Level of the 16Mb MRAM in the 48-BGA Package Upgraded to MSL-3.pdf
The 16Mb MRAM in the 48-BGA is being upgraded from MSL-5 to MSL-3.
PCN02969 Add Amkor Philippines as a Subcontractor Assembly Site for the DFN small flag package.pdf
PCN02954 Moisture Sensitivity Level of the 16Mb MRAM in the 48-BGA Package Upgraded to MSL-5.pdf
The moisture sensitivity level for these products was previously stated as MSL-6 as of March 22, 2016 in PCN 02941. This PCN is to notify customers that the moisture sensitivity level is upgraded to MSL-5. This improvement is the result of package materials and process optimization in conjunction with Everspin assembly subcontractor UTAC Dongguan.
Add ChipMOS as a Subcontractor Assembly Site for 16Mb(x16) 54p TSOP2 package.v1.pdf
PCN02952 Add OSE Assembly Site for 1Mb(x16) and 4Mb (x8and x16) BGA Package.pdf
Everspin is adding OSE as a qualified assembly site for the 1Mb(x16) and 4Mb (x8 and x16) MRAM BGA package.
PCN02941 Moisture Sensitivity Level of the 16Mb MRAM in the 48-BGA Package.pdf
PCN02934 ASE-M DFN for 4Mb SPI Product.pdf
Everspin Technologies, Inc. has approved ASE-Malaysia as a qualified source of the DFN package used on the MR25H40 4Mb SPI family of products. Everspin will consider this change accepted unless specific conditions for acceptance are provided in writing within 30 days of receipt of this notice.
Product Discontinuance of 32-SOIC Package
PCN02784 Mold Compound Change for 44pin TSOP2 for ASE-KH
To improve flexibility in manufacturing Everspin has qualified the 44 pin TSOP2 package from ASE-KH (Kaohsiung) with a new mold compound, G631H. This mold compound is already in use at other assembly sites.
PCN02370 Everspin is adding ASE-Malaysia as a qualified assembly site
In order to increase capacity and improve supply flexibility, Everspin is adding ASE-Malaysia as a qualified assembly site for 16Mb MRAM products in the 48-BGA package.
PCN02756 Adding ASE Malaysia as a Qualfied Assembly Site on 16Mb BGA Product_final_C.pdf
Everspin is adding ASE-Malaysia as a qualified assembly site for 16Mb MRAM products in the 48-BGA package.
PCN02693A Add OSE as a qualified assembly subcontractor
To increase production capacity and improve flexibility in manufacturing Everspin has qualified an additional subcontractor, OSE, for assembly of the TSOP- 44 package.
PCN02542 Add TICP as a qualified source of the 16Mb X8 in the TSOP2 package
To increase production capacity and improve flexibility in manufacturing Everspin has qualified TICP as an additional assembly location for the 16Mb (x8) MRAM.
PCN02257 Everspin adds UTAC Dongguan (UDG) as a qualified source of the BGA package
Everspin adds UTAC Dongguan (UDG) as a qualified source of the BGA package
PCN20120628_0 A - Everspin qualifies ASE Malaysia as an assembly source for 256Kb and 1Mb MRAM in the BGA package
Everspin adds ASE Malaysia as a qualified source for BGA package assembly of 256Kb and 1Mb MRAM.
PCN1893 ALTERNATIVE FORMAT FOR TRACE CODES ON PACKAGE MARKING
Beginning December 30, 2011, Everspin may use an alternative Trace Code marking format interchangeably with the existing format. The existing format identifies fabrication site, assembly site, final test site and wafer lot, year and work week. The alternative format will identify the assembly site and wafer lot, year and work week. Affects all Everspin products and packages.
ASE QUALIFIED AS ADDITIONAL TSOP ASSEMBLY SITE
Everspin has qualified nine additional products for TSOP assembly at assembly subcontractor ASE. PCN date August 19, 2011, effective November 18, 2011
Burn-In, Final Test transferred to UTAC Taiwan for 256Kb, 1Mb, 4Mb Parallel IO and 256Kb and 1Mb Serial SPI MRAM
Burn-in, final test and end of line services are transferred from UTAC Singapore to UTAC Taiwan.
Add ASE as a qualified assembly subcontractor for 256Kb and 1Mb MRAM in TSOP2 packages
Add ASE (in addition to Freescale KLM) as a qualified assembly subcontractor.
Everspin Product Marking
Product marking change from Freescale logo to Everspin logo for 16 bit parallel IO family.
TSPG MCD MRAM MR2A16A MASK REVISION
Freescale is announcing improved MRAM MR2A16ATS35C devices.
FREESCALE PRODUCT BULLETIN 12665
TSPG MCD MR2A16A TEST AND B/I EXPANSION
packaging
Everspin_24-ball_BGA_MRAM_Packages.pdf
24-ball BGA Package Guide for Everspin Toggle MRAM products
Everspin_48-ball BGA_Package_Guide.pdf
Thermal Resistance, Recommended reflow profile, package outline drawings for all 48-ball FBGA packages from Everspin
Everspin TSOP2 Package Guide.pdf
Thermal Resistance, Recommended reflow profile, package outline drawings for all TSOP2 packages from Everspin
EST02153_Everspins Small Flag DFN Replaces SOIC Package_AppNote_Rev5 041413.pdf
product notes
SLM02691_Everspin_Product_Discontinuance.pdf
Everspin Product Discontinuation notice
Automotive Product Brief 112415a.pdf
Everspin MRAM is an ideal memory for automotive applications.
- Save data at full bus speed.
- Instantly restore status after an unexpected power loss.
- AEC-Q100 Qualified Grades 1 and 3 available.
PNT02190 8-pin DFN Package with Reduced Exposed Pad Size Recommended for New Designs
PNT02190 8-pin DFN Package with Reduced Exposed Pad Size Recommended for New Designs
PNT02203 Product Note - Magnetic Immunity improvement on 1Mb (x16) and 4Mb (x16 and x8) TSOP2 Industrial and Extended Temp grades
PNT02203 Product Note - Magnetic Immunity improvement on 1Mb (x16) and 4Mb (x16 and x8) TSOP2 Industrial and Extended Temp grades
application notes
EST 2130 Comparing_Technologies_FRAM_vs_MRAM_AppNote.pdf
Comparing MRAM to FRAM
EST 2909 Replacing the Fujitsu MB85R8M2T FRAM with Everspin’s MR3A16Axxx MRAM.pdf
Replacing the Fujitsu MB85R8M2T FRAM with Everspin’s MR3A16Axxx MRAM.v1
EST 2911 Replacing the Cypress CY62137EV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.pdf
EST 2911 Replacing the Cypress CY62137EV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.v1
EST 2912 Replacing the Cypress CY62137FV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.pdf
EST 2912 Replacing the Cypress CY62137FV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.v1
EST 2913 Replacing the Cypress CY62137FV18LL MoBL SRAM with Everspins MR1A16Axxx MRAM.pdf
EST 2913 Replacing the Cypress CY62137FV18LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM
EST 2904 Replacing the Cypress CY15B102N-ZS60XA FRAM with Everspin MR1A16AxYS35 MRAM.pdf
EST 2904 Replacing the Cypress CY15B102N-ZS60XA FRAM with Everspin MR1A16AxYS35 MRAM
EST 2905 Replacing the Cypress FM28V202A-TG FRAM with Everspin MR1A16AxYS35 MRAM.pdf
EST 2905 Replacing the Cypress FM28V202A-TG FRAM with Everspin MR1A16AxYS35 MRAM
EST 2906 Replacing the Cypress CY62136EV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.pdf
EST 2906 Replacing the Cypress CY62136EV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM
EST 2907 Replacing the Cypress CY62136FV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.pdf
EST 2907 Replacing the Cypress CY62136FV30LL MoBL SRAM with Everspin’s MR1A16Axxx MRAM
EST 2908 Replacing the Cypress CY62136ESL MoBL SRAM with Everspin’s MR1A16Axxx MRAM.pdf
EST 2908 Replacing the Cypress CY62136ESL MoBL SRAM with Everspin’s MR1A16Axxx MRAM
Medical Ventilator Application Note
Medical ventilator application note
EST 2901 Replacing Cypress CY62177EV30 MoBL SRAM with Everspin MR5A16Axxx35 MRAM.pdf
Replacing Cypress CY62177EV30 MoBL SRAM with Everspin MR5A16Axxx35 MRAM
EST 2902 Replacing the Cypress CY62168EV30LL-45BVXI MoBL SRAM with Everspin MR4A08B MRAM.pdf
EST 2902 Replacing the Cypress CY62168EV30LL-45BVXI MoBL SRAM with Everspin MR4A08B MRAM
EST 2900 Replacing Cypress CY14B108N nvSRAM with Everspin MR3A16Axxx35 MRAM.pdf
EST 2900 Replacing Cypress CY14B108N nvSRAM with Everspin MR3A16Axxx35 MRAM
Enabling Xilinx FPGA Controllers for ST-DDR4 Persistent Memory
Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a persistent memory technology that delivers performance, persistence, and durability utilizing variants of industry standard interfaces. Everspin has introduced STT-MRAM products that utilize a variant of the JEDEC standard DDR4 interface, called ST-DDR4, that encompasses the unique functionality required for full system support. This document will help engineers understand how to enable a Xilinx FPGA memory controller to communicate with persistent ST-DDR4 memory.
ST-DDR4 Change Table V1 0.pdf
This app note shows the names of the fifteen modules that require changes from the standard Xilinx MIG controller for a XCKU060-2FFVA1156E device. When run properly, the example script will automate these changes for the user.
ST-DDR3_Design_Guide_for_Xilinx_FPGA_Controllers.pdf
ST-DDR3 Design Guide for Xilinx FPGA Controllers
Application Note Utilizing Everspin STT-MRAM in Enterprise SSDs
As Enterprise Solid State Drives (SSDs) continue to push the envelope in terms of system performance and smaller form factors, SSD solutions providers are facing greater challenges to increase performance and density while continuing to protect data-in-flight from power failures. NAND flash has not significantly increased in performance and the improvement in SSD performance is typically made by adding more parallel channels of flash. This increases the need for energy storage for power fail protection which in turn reduces space available for the storage array for a fixed form factor.
This application note explores the SSD architecture benefits of employing Everspin ST-MRAM on the DDR bus of the SSD controller to provide a high speed, non-volatile write buffer in order to reduce power fail energy storage while increasing performance and storage density.
Accelerating Fintech Applications with Lossless and Ultra-Low Latency Synchronous Logging using nvNITRO
Financial Technology (FinTech) companies are looking for performance increases that still enable them to remain in compliance by protecting data. The nvNITRO accelerator with MRAM memory can increase performance 9X by dramatically reducing latency, all while protecting the data with persistence and endurance.
Replacing the CypressCY14B101LA-xx nvSRAM with Everspin's MR0A08Bxxx MRAM
Considerations for replacing nvSRAM with MRAM
EST02058_Replacing the Cypress CY14B256LA nvSRAM with Everspin MR256A08B MRAM Rev 2 080615 (2).pdf
Replacing the Cypress CY14B256LA nvSRAM with Everspin MR256A08B MRAM
Considerations for replacing nvSRAM with MRAM
EST02852 Replacing the Cypress CY14V256LA_BA35 nvSRAM with Everspins MR256D08BMA45 MRAM 032015.pdf
Replacing the Cypress CY14U256LA-BA35 nvSRAM with Everspin's MR256DL08BMA45 MRAM
Replacing the Cypress CY14U256LA-BA35 nvSRAM with Everspin's MR256DL08BMA45 MRAM
Replacing MR20H40DF commercial temperature grade part with MR20H40CDF industrial temperature grade
To simplify product selection and improve manufacturing efficiency, Everspin will discontinue the MR20H40DF (Commercial grade) and replace it with the MR20H40CDF (Industrial grade).
Replacing the Cypress CY14V101LA-BA45 nvSRAM with Everspin's MR0D08BMAxx MRAM
The Everspin MR0D08BBMA45 MRAM memory is pin and timing compatible with the Cypress CY14V101LA-BA45 nvSRAM.
Replacing Cypress CY14B104LA_BA and ZS nvSRAMs with Everspin MR2A08B MRAM
Replacing Cypress CY14B104LA_BA and ZS nvSRAMs with Everspin MR2A08B MRAM
Replacing Cypress CY14B104NA BA and ZS nvSRAMs with Everspin MR2A16A MRAM
Replacing the Cypress CY14B104NA-BA/ZS45XI nvSRAM with Everspin's MR2A16Axxx35 MRAM
Replacing the Cypress CY14B108LA-xx 8Mb nvSRAM with Everspin's MR4A08Bxxx 16Mb MRAM
Replacing 8Mb nvSRAM with 16Mb MRAM in TSOP2 and FBGA packages.
Using a Single Vdd pin for the MR0D08BMA45
Describes the use of a single VDD supply for the MR0D08B MRAM Family in 48-BGA packages.
Approximating the Magnetic Field When Using Everspin MRAM
How to create an approximation of the magnetic field strength surrounding an MRAM
EVERSPIN's New 2mm Exposed Pad DFN Package Meets Both SOIC-8 and DFN8 PCB Layouts
Replacing SRAM in SOIC or DFN package with MRAM in DFN
Quad SPI Evaluation Boards
MR10Q010 Quad SPI Evaluation Board Guide
MR10Q010 Quad SPI Evaluation Board Guide
MR25H00-EVAL SPI Evaluation Board Guide Revision 1 022416b.pdf
MR10Q010 Quad SPI Evaluation Board Guide Revision 1 022416.pdf
MR10Q010 Quad SPI Evaluation Board Guide Revision 1
MR10Q010 in 3.3v. I/O System Evaluation Board
Adapting MR10Q010 for Operation in a 3.3v I/O System
MRAM Example Code for Evaluation EVAL Board.zip
Example MRAM Code for the MR10Q010EVAL Evaluation Board
MR10Q010-EVAL Board Layout and Schematic.pdf
MR10Q010 Evaluation Board Layout and Schematic
technical articles & white papers
Cobham_MRAM_Qual_and_Reliability_paper 2020.pdf
Cobham Toggle MRAM Quality and Reliability White Paper
Toggle MRAM Quality and Reliability Paper
A white paper discussing the reliability and qualification for Toggle MRAM components by Cobham
MRAM Improvements to Automotive Non-Volatile Memory Storage
Automotive powertrain modules use flash memory technology to retain critical control and diagnostic information during power off (keep-alive memory (KAM) and non-volatile memory (NVM)). Complex software must be designed to maximize the lifecycle of these devices because they have a limited number of write cycles. MRAM (Magneto resistive Random Access Memory) has the potential to eliminate this complexity and make the process of managing KAM and NVM easier and more robust. This paper demonstrates using off-board MRAM devices with a next generation of powertrain microprocessor. The prototype boards integrating the latest powertrain microcontroller, with the Everspin MRAM MRA16A (2 pcs of x16 bits) and MR2xH50 (@ a SCK 40MHz) chips were created. An investigation was performed evaluating the MRAM capabilities for storing and retrieving data during simulated key-off and key-on events.
Toggle and Spin-Torque MRAM: Status and Outlook
Article by J.M. Slaughter, et.al., of Everspin Technologies
IBIS Model
MR256A08BCYS35 IBIS File.
Ibis model for part MR256A08BCYS35.
MR10Q010 IBIS File for 16-SOIC.ibs
IBIS file for part MR10Q010CSC in 16-SOIC. Revision 0, dated March 23, 2015
verilog model
MR10Q010 Quad SPI MRAM Verilog Model
This is the VERILOG model of the MR10Q010. MR10Q010.V is the abstracted model of a 128K x 8 MRAM. The following is contained in the download:
1. Readme_MR10Q010 - Overview
2. MR10Q010.V - MR10Q010 1Mb QSPI MRAM behavioral model
3. Config_MR10Q010.VH - parameters file for the model
4. sim/run_sim - script to run simulation using NC-Verilog
5. sim/tb_mr10q010.v - test bench
MR4A16B_verilog_model_1.1.zip
This is the VERILOG model of the MR4A16B. MR4A16B.V is the abstracted model of a 1Mb x 16 MRAM. The following is contained in the download: 1. Readme_MR4A16B - Overview 2. MR4A16B.V - Device Model 3. Config_MR4A16B.V - Configuration File
MR0A16A VERILOG Model
This is the VERILOG model of the MR0A16A. MR0A16A.V is the abstracted model of a 64K x 16 MRAM. The following is contained in the download:
1. Readme_MR0A16A - Overview
2. MR0A16A.V - Device Model
3. Config_MR0A16A.V - Configuration File
4. testbench_MR0A16A.v - Test bench file
MR2A16A VERILOG Model
This is the VERILOG model of the MR2A16A. MR2A16A.V is the abstracted model of a 256K x 16 MRAM. The following is contained in the download:
1. Readme_MR2A16A - Overview
2. MR2A16A.V - Device Model
3. Config_MR2A16A.V - Configuration File
4. testbench_MR2A16A.v - Test bench file
MR2A08A VERILOG Model
This is the VERILOG model of the MR2A08A. MR2A08A.V is the abstracted model of a 512K x 8 MRAM. The following is contained in the download:
1. Readme_MR2A08A - Overview
2. MR2A08A.V - Device Model
3. Config_MR2A08A.V - Configuration File
MR4A08B VERILOG Model
This is the VERILOG model of the MR4A08B. MR4A08B.V is the abstracted model of a 2Mb x 8 MRAM. The following is contained in the download:
1. Readme_MR4A08B - Overview
2. MR4A08B.V - Device Model
3. Config_MR4A08B.V - Configuration File
MR25H256 VERILOG Model
This is the VERILOG model of the MR25H256. MR25H256.V is the abstracted model of the 256Kb SPI MRAM. The following is contained in the download:
1. Readme_MR25H256 - Overview
2. MR25H256.V - Device Model
3. Config_MR25H256.V - Configuration File
MR256A08B VERILOG Model
This is the VERILOG model of the MR256A08B. MR256A08B.V is the abstracted model of a 32K x 8 MRAM. The following is contained in the download:
1. Readme_MR256A08B - Overview
2. MR256A08B.V - Device Model
3. Config_MR256A08B.V - Configuration File
MR25H10 VERILOG Model
This is the VERILOG model of the MR25H10. MR25H10.V is the abstracted model of the 1Mb SPI MRAM. The following is contained in the download:
1. Readme_MR25H10 - Overview
2. MR25H10.V - Device Model
3. Config_MR25H10.V - Configuration File
MR0A08B VERILOG Model
This is the VERILOG model of the MR0A08B. MR0A08B.V is the abstracted model of a 128K x 8 MRAM. The following is contained in the download:
1. Readme_MR0A08B - Overview
2. MR0A08B.V - Device Model
3. Config_MR0A08B.V - Configuration File
VHDL model
MR4A16B VHDL Model
This is the VHDL model of the MR4A16B. This is a high level abstraction of this product. The following is contained in the download: 1. Readme_MR4A16B 2. MR4A16B.vhdl - Device Model 3. Package_Utility - Standard Conversion Utilities 4. Benchtest.vhdl - Top Level Test Bench 5. MR4A16B_Driver.vhdl - Sample Test Vectors used for the Verification 6. MR4A16B.txt - Memory Initialization File
MR25H10 VHDL Model
This is the VHDL model of the MR25H10. This is a high level abstraction of this product. The following is contained in the download:
1. Readme_MR25H10
2. MR25H10.vhdl - Device Model
3. Package_Utility - Standard Conversion Utilities
4. Benchtest.vhdl - Top Level Test Bench
5. MR25H10_Driver.vhdl - Sample Test Vectors used for the Verification
6. MR25H10.txt - Memory Initialization File
MR25H256 VHDL Model
This is the VHDL model of the MR25H256. This is a high level abstraction of this product. The following is contained in the download:
1. Readme_MR25H256
2. MR25H256.vhdl - Device Model
3. Package_Utility - Standard Conversion Utilities
4. Benchtest.vhdl - Top Level Test Bench
5. MR25H256_Driver.vhdl - Sample Test Vectors used for the Verification
6. MR25H256.txt - Memory Initialization File
MR2A16A VHDL Model
This is the VHDL model of the MR2A16A. This is a high level abstraction of this product. The following is contained in the download:
1. Readme_MR2A16A
2. MR2A16A.vhdl - Device Model
3. Package_Utility - Standard Conversion Utilities
4. Benchtest.vhdl - Top Level Test Bench
5. MR2A16A_Driver.vhdl - Sample Test Vectors used for the Verification
6. MR2A16A.txt - Memory Initialization File
MR256A08B VHDL Model
This is the VHDL model of the MR256A08B. This is a high level abstraction of this product. The following is contained in the download: 1. Readme_MR256A08B 2. MR256A08B.vhdl - Device Model 3. Package_Utility - Standard Conversion Utilities 4. Benchtest.vhdl - Top Level Test Bench 5. MR256A08B_Driver.vhdl - Sample Test Vectors used for the Verification 6. MR256A08B.txt - Memory Initialization File
MR0A08B VHDL Model
This is the VHDL model of the MR0A08B. This is a high level abstraction of this product. The following is contained in the download: 1. Readme_MR0A08B 2. MR0A08B.vhdl - Device Model 3. Package_Utility - Standard Conversion Utilities 4. Benchtest.vhdl - Top Level Test Bench 5. MR0A08B_Driver.vhdl - Sample Test Vectors used for the Verification 6. MR0A08B.txt - Memory Initialization File
MR2A08A VHDL Model
This is the VHDL model of the MR2A08A. This is a high level abstraction of this product. The following is contained in the download:
1. Readme_MR2A08A
2. MR2A08A.vhdl - Device Model
3. Package_Utility - Standard Conversion Utilities
4. Benchtest.vhdl - Top Level Test Bench
5. MR2A08A_Driver.vhdl - Sample Test Vectors used for the Verification
6. MR2A08A.txt - Memory Initialization File
RoHS / REACH
Everspin Conflict Minerals Report Fiscal 2019.pdf
Everspin Conflict Minerals Report Fiscal 2019
Everspin_RoHS_Red_Phosphorus_Compliance.pdf
RoHS Red Phosphorous statement
Everspin_CFSI_CMRT 5_01_Product Level_10_26_17.xlsx
Everspin CFSI CMRT Product-level Template
Everspin_CFSI_CMRT 5_01_Company Level_10_26_17.xlsx
Everspin CFSI CMRT Company-level Template